How HDI Technology Enables the Miniaturization of Modern Electronics

Open any smartphone, peel back the EMI shield, and look at the main PCB. What you see is a board roughly the size of a credit card carrying an application processor with 2,000+ solder balls on 0.35 mm pitch, 8–16 GB of LPDDR memory in a package-on-package stack, a mmWave antenna module, hundreds of 0201 and 01005 passive components, and dozens of high-speed differential pairs routing between them—all on 10 or more layers with feature sizes that were considered advanced semiconductor geometry a generation ago. That board is an HDI (High-density Interconnect) PCB, and without Hdi Technology, the device you are holding would be the size of a brick.

HDI is not a single innovation but a suite of manufacturing capabilities—Microvias, fine lines, build-up layers, Via-in-pad, and any-layer interconnect—that together enable the component density, routing density, and signal-integrity performance that modern electronics demand. This article examines how each of these capabilities works, why they matter, and how they are transforming product design across industries.

What Makes HDI Different from Conventional PCBs

A conventional PCB (sometimes called a "through-hole multilayer" or THML board) uses plated through-holes (PTHs) to connect layers. A 1.0 mm diameter PTH on a 1.6 mm board consumes a via pad on every layer plus an Annular Ring—typically 2.0–2.5 mm total diameter on every layer, whether that layer needs the connection or not. On a dense board, PTHs consume 40–60 % of available routing area, creating a "Swiss cheese" effect that limits how many traces can route between vias.

Hdi Boards replace large PTHs with Microvias—small-diameter, short-depth vias that connect only adjacent layers. A typical Microvia is 0.1 mm diameter, connecting two adjacent layers over a 0.05–0.1 mm dielectric. Because it is small and local, it consumes minimal routing area on other layers. The result: dramatically higher interconnect density, finer routing channels, and the ability to escape-route from fine-pitch BGAs that would be impossible on a THML board.

The IPC-2226 standard defines Hdi Boards by their feature sizes and via structures:

• Type I: One Microvia layer on each side of a core, with through-holes through the core. The simplest HDI construction.
• Type II: One microvia layer on each side, with staggered or Stacked Microvias through the build-up layers plus through-holes through the core.
• Type III: Two or more microvia layers on each side, enabling higher via density and more routing layers in the build-up. Common in smartphones and high-end tablets.
• Type IV (Any-layer Hdi): Every layer pair is connected by microvias; there are no through-holes. The ultimate in interconnect density, used in the most advanced mobile and wearable products.

Microvias: The Key That Unlocks Density

How Microvias Are Made

Unlike through-holes, which are drilled mechanically, microvias are created by Laser Drilling. A UV or CO₂ laser ablates a small hole through the dielectric layer to expose the target pad on the layer below. The hole is then desmeared (removing residual dielectric resin from the copper target) and metallized—typically by electroless copper deposition followed by electrolytic Copper Plating, or by conductive-ink fill followed by planarization.

Laser-drilled microvia capability defines what a fab can produce:

• CO₂ laser: Typically produces 0.1–0.15 mm diameter vias in organic dielectrics. Limited to ablation of resin and glass—cannot drill through copper. The copper on the target layer must be "conformal mask" opened (etched away at the via location) before lamination.
• UV laser (355 nm or 266 nm): Can drill through copper as well as dielectric, enabling "direct drill" where the laser opens the via through both the dielectric and the target copper in one step. UV lasers achieve smaller via diameters (0.06–0.10 mm) but at slower drilling speed.
• Combined UV/CO₂: Many modern HDI lasers use a UV beam to drill through the top copper and a CO₂ beam to ablate the dielectric—combining the precision of UV for the copper with the speed of CO₂ for the dielectric.

Filled and Capped Microvias

For Via-in-pad construction (where a component pad sits directly over a via), the microvia must be filled with copper or epoxy-copper paste and planarized flat. Unfilled vias under BGA pads would wick solder away from the joint during reflow, creating open or weak connections. Via Filling adds process steps (fill, planarize, cap-plating) but is essential for fine-pitch BGA breakout routing.

Stacked vs. Staggered Microvias

• Stacked Microvias place vias directly on top of each other across multiple layer pairs. This provides the shortest possible interlayer connection—critical for minimizing via parasitics in high-speed paths. Stacked vias require filled-and-capped construction at each level, adding cost.
• Staggered microvias offset each via from the one below, connecting with a short trace segment. Simpler to manufacture (no fill required on intermediate levels) but slightly longer interconnect and higher parasitic inductance.

For most high-speed applications, stacked microvias are preferred for their lower parasitic inductance (typically 0.2–0.4 nH per via vs. 0.5–0.8 nH for staggered with a short trace). The difference matters at 10+ Gbps, where via parasitics can degrade Signal Integrity.

Fine-Line Routing: Pushing the Limits of Trace Width and Spacing

HDI boards routinely use trace widths and spaces of 3/3 mil (0.075/0.075 mm) or even 2/2 mil (0.050/0.050 mm) in the build-up layers. This compares to 4/4 or 5/5 mil on conventional boards. Fine-line routing is what allows HDI to escape-route from 0.4 mm pitch BGAs with room to spare.

Manufacturing Challenges at Fine Lines

• Etch control. At 2 mil traces, a 0.3 mil over-etch represents a 15 % width reduction—enough to significantly affect impedance and current capacity. Semi-additive process (SAP) or modified semi-additive process (mSAP) is used for fine lines: a thin seed layer is plated, photoresist is patterned, and copper is electrolytically plated only on the trace areas. The seed layer is then flash-etched away. SAP/mSAP produces finer, more uniform traces than subtractive etching.
• Copper weight. Fine lines require thin copper—typically ⅓ oz (12 µm) or ½ oz (17 µm) on build-up layers. Standard 1 oz copper cannot be etched to 2 mil lines with acceptable dimensional control.
• Registration. At 3/3 mil lines, layer-to-Layer Registration must be within ±0.05 mm (2 mil). This requires direct imaging (DI) systems—laser-based exposure tools that align to fiducials on each panel with sub-micron accuracy—rather than contact film exposure.

Routing Density Gains

The combination of microvias and fine lines multiplies routing density. On a conventional 4/4 mil board with through-holes, a 0.5 mm pitch BGA typically allows one trace between via pads (sometimes called "1-line channel"). On an HDI board with 3/3 mil lines and microvias, the same BGA allows two or three traces between via pads. This is the difference between a routable and an unroutable design.

Build-Up Lamination: Adding Layers Where They Are Needed

HDI boards are built in a fundamentally different sequence from conventional multilayer boards. Instead of laminating all layers at once, HDI uses a sequential build-up process:

1. Core fabrication. The inner core (typically 2–4 layers) is fabricated using conventional inner-layer imaging, etching, and lamination.
2. First build-up layer. A layer of prepreg (or RCC—resin-coated copper) is laminated onto one or both sides of the core. Microvias are laser-drilled through the build-up dielectric to connect to the core. The build-up layer is imaged, etched, and plated.
3. Second build-up layer. Another dielectric layer is laminated on, microvias are drilled (connecting to the first build-up layer), and the process repeats.
4. Repeat for additional build-up layers (Type III HDI may have 2–3 build-up layers per side).
5. Outer-layer processing. Solder mask, surface finish, and edge-finish are applied to the completed stack.

Each build-up lamination cycle adds cost and cycle time. A Type I HDI (one build-up per side) adds one lamination cycle. A Type III HDI (two build-ups per side) adds two. An Any-layer Hdi with N layers adds N−2 cycles. This is why HDI is more expensive than THML—but the cost is justified when the alternative is a larger board or a product that cannot meet its size target.

Via-in-Pad: The Secret to Fine-Pitch BGA Breakout

On a conventional board, BGA pads cannot have vias in them—vias are placed in the "dog-bone" area between pads, with a short trace connecting the pad to the via. At 0.5 mm pitch, the dog-bone area is barely large enough for a 0.25 mm via. At 0.4 mm pitch, it is impossible—the via must go in the pad.

Via-in-pad (VIP) places a filled microvia directly in the BGA land pad. The via connects the pad to the target layer without any routing channel on the component side. This:

• Eliminates the dog-bone trace, freeing routing area on the component layer.
• Reduces the stub length from the BGA pad to the via, improving Signal Integrity for high-speed links.
• Enables breakout routing from 0.4 mm and 0.35 mm pitch BGAs that would otherwise require a larger board or an interposer.

VIP requires filled-and-capped microvias (as described above) and careful thermal design—the via conducts heat away from the BGA joint, which can affect solder-joint reliability for components with low thermal mass. Simulation and reliability testing are recommended for VIP under 0.4 mm pitch components in thermally demanding applications.

HDI in Practice: Applications Across Industries

Smartphones and Tablets

The smartphone is the canonical HDI application. A flagship phone main board is typically a 10–14 layer any-layer HDI with:

• 0.35 mm pitch application-processor BGA with 1,000+ balls, routed via VIP.
• 3/3 mil or 2.5/2.5 mil traces in build-up layers.
• 01005 passive components on 0.2 mm placement grid.
• Multiple RF front-end modules with controlled-impedance microstrip and coplanar waveguide.
• Board thickness of 0.8–1.0 mm to fit within the phone chassis.

Without any-layer HDI, a phone board of equivalent functionality would be 3–5× larger—unacceptable in a market where every millimeter of device thickness is competitive advantage.

Wearable and Hearable Devices

True wireless earbuds, smartwatches, and AR glasses push HDI further—into boards under 10 mm × 20 mm with 6–8 layers and 2/2 mil lines. These ultra-small HDI boards often use embedded components (passives buried in inner layers) to further reduce surface area. The via density is extreme: some wearable HDI boards have over 10,000 microvias per square centimeter.

Medical Implantable Devices

Pacemakers, neurostimulators, and cochlear implants use HDI to maximize functionality within the smallest possible hermetic package. A modern pacemaker PCB is a 6–8 layer HDI board under 30 mm × 20 mm, carrying a system-on-chip, telemetry antenna, sensing channels, and therapy output stages. HDI enables the routing density needed to interconnect these functions in the limited board area, while the thin build-up construction helps meet the package-height constraint of a subcutaneous implant.

Automotive ADAS and Domain Controllers

Automotive Electronics are not yet at smartphone-level HDI density, but the trend is accelerating. Adas domain controllers—centralized compute platforms that process data from radar, camera, and lidar sensors—are migrating from 6–8 layer THML boards to 10–12 layer Type II/III HDI boards. The driver is the processor: NVIDIA Orin, Qualcomm Ride, and similar SoCs come in 0.4 mm pitch BGAs with 1,500+ balls. Routing these on a THML board requires an unacceptably large board or a processor package with fewer I/O (sacrificing performance). HDI provides the escape routing density in the board area that the vehicle packaging allows.

5G and mmWave Modules

5G new-radio modules operate at 28 GHz and 39 GHz, requiring antenna-in-package (AiP) or antenna-on-board constructions with precise controlled-impedance routing and tight dielectric thickness control. HDI build-up layers provide the thin, controlled dielectrics (50–100 µm) needed for mmWave microstrip and stripline structures—thicknesses that are difficult to achieve in a conventional core-based stack-up. The microvias connecting the antenna elements to the RF transceiver must have minimal parasitic inductance, favoring stacked microvias in the feed network.

Design Rules and Trade-offs in HDI

HDI design involves a different set of trade-offs than conventional Pcb Design:

• Number of build-up layers vs. cost. Each build-up layer adds a lamination cycle, drilling cycle, and plating cycle. Moving from Type I to Type III roughly doubles the via-related cost. The design should use the minimum HDI construction that can route the board—adding build-up layers only where routing density demands it.
• Via diameter vs. aspect ratio. The aspect ratio (dielectric thickness / via diameter) should not exceed 1.0 for reliable plating. A 0.1 mm via in a 0.1 mm dielectric has aspect ratio 1.0—platable with good process control. A 0.1 mm via in a 0.15 mm dielectric (aspect ratio 1.5) is marginal and may require pulse-reverse plating to achieve center-fill.
• Trace width vs. Impedance Control. Fine lines have less impedance margin for etch variation. At 3 mil traces on ½ oz copper, a 0.3 mil etch error is 10 %—translating to roughly 5 % impedance error. If ±5 % Impedance Tolerance is required, the trace width and dielectric thickness must be tightly controlled.
• Board thickness vs. rigidity. HDI boards are often thin (0.6–1.0 mm for mobile, 0.4–0.6 mm for wearable). Thin boards are less rigid and more prone to warpage during assembly. Panel stiffeners, support rails, and fixture design must account for this.

Manufacturing Capability: What to Look for in an HDI Fab

Not every PCB manufacturer can produce HDI boards, and the capability range varies widely. When evaluating an HDI fabricator, assess:

• Microvia capability. Minimum via diameter, maximum aspect ratio, and via fill capability (copper fill, epoxy-copper paste, or conductive ink). Ask for reliability data—via-chain resistance after IST (interconnect stress test) per IPC-TM-650 2.6.26.
• Line/space capability. Minimum finished trace width and spacing on build-up layers. Confirm whether they use SAP/mSAP or subtractive etch for fine lines—SAP/mSAP is strongly preferred for 3/3 mil and below.
• Any-layer via capability. Can they produce any-layer stacked microvias? This is the most demanding HDI process and is not available at all fabs.
• Build-up lamination experience. How many sequential laminations have they demonstrated in production? A fab that has only built Type I HDI should not be trusted with Type III or any-layer.
• Direct imaging (DI). Laser DI is required for fine-line imaging with the registration accuracy that HDI demands. Contact-film exposure cannot hold the tolerances.
• Reliability testing. IST, HATS (highly accelerated thermal shock), and thermal cycling data for microvia chains, via-in-pad structures, and the complete stack-up. Hdi Reliability is less mature than THML reliability—data matters.

The Future of HDI: Where Density Goes Next

The demand for Miniaturization shows no sign of abating, and Hdi Technology continues to evolve to meet it:

• Sub-2 mil lines. 1.5/1.5 mil (38/38 µm) is entering pilot production for next-generation mobile processors. This requires mSAP with 10 µm or thinner copper and DI tools with sub-micron stage accuracy.
• Embedded components. Buried passives (resistors, capacitors) and embedded actives (discrete die) eliminate surface area and shorten interconnects. Embedded technology is moving from specialty to mainstream HDI, particularly for wearable and medical devices where every square millimeter matters.
• Semi-additive on any layer. The convergence of mSAP fine-line capability with any-layer via structures will produce boards where every layer is a build-up layer—no core at all. This "coreless" construction maximizes routing density and minimizes board thickness.
• Optical interconnect on HDI. Embedded optical waveguides in HDI build-up layers are being developed for chip-to-chip optical links at 100+ Gbps. The thin, controlled dielectrics of HDI are well-suited to polymer optical waveguide fabrication.
• 3D-printed interconnect. Additive manufacturing of copper interconnect on dielectric substrates is a research-stage technology that could eventually bypass conventional etching entirely—building only the copper that is needed, where it is needed, with zero waste.

Conclusion

HDI technology is the enabler of modern electronics Miniaturization—not a luxury but a necessity for any product that must pack high functionality into a small space. Microvias, fine lines, build-up laminations, and via-in-pad construction work together to provide interconnect density that conventional through-hole multilayer boards cannot approach. The result is smaller products, higher performance (shorter interconnects mean better signal integrity), and new form factors that were literally impossible before HDI.

The cost premium of HDI over conventional boards is real but often overstated. For many designs, HDI is the only way to route the board in the available area—and the alternative (a larger board, a larger product, or a less capable processor) is far more costly. As component pitches continue to shrink and interconnect counts continue to rise, HDI is not just the best option—it is the only option that scales.

For HDI PCB Fabrication with any-layer microvia capability, fine-line SAP/mSAP processes, and proven reliability data, contact our HDI engineering team to discuss your stack-up and routing requirements.

FAQ

What is the difference between HDI and conventional PCBs?

HDI boards use microvias (laser-drilled, small-diameter vias connecting adjacent layers) and fine trace widths (3 mil or below) instead of the large through-holes and wider traces of conventional boards. This dramatically increases routing density, enabling finer-pitch component breakout and smaller board sizes.

What is an any-layer HDI board?

Any-layer HDI (Type IV) connects every layer pair with microvias—there are no through-holes spanning the entire board. This provides the highest interconnect density and is used in the most advanced smartphones and wearable devices.

Why are microvias better than through-holes for high-speed signals?

Microvias have much lower parasitic inductance (0.2–0.4 nH vs. 0.5–1.5 nH for through-holes) because of their smaller diameter and shorter length. Lower inductance means less signal degradation at high frequencies, improving eye-diagram margin at multi-gigabit data rates.

What is via-in-pad and why is it needed?

Via-in-pad places a filled microvia directly inside a BGA land pad, eliminating the "dog-bone" trace that connects the pad to a nearby via. It is required for BGA pitches of 0.5 mm and below, where there is no space between pads for a separate via and connecting trace.

How much more does HDI cost than conventional PCBs?

Cost depends on the HDI type and layer count. Type I HDI (one build-up per side) typically adds 20–30 % over a comparable THML board. Type III HDI adds 50–80 %. Any-layer HDI can cost 2–3× a conventional board. However, HDI often eliminates the need for a larger board or an interposer, so system-level cost may be lower.