The Impact of Via-in-Pad on Thermal Performance and Reliability

Via-in-pad — placing a via directly within a component land pad rather than beside it — is one of the most consequential design decisions in modern PCB layout. It affects thermal performance, solder joint integrity, manufacturing cost, and long-term reliability in ways that are not always obvious from a schematic view. Done correctly, Via-in-pad dramatically improves heat extraction from power components. Done incorrectly, it creates solder defects that undermine the very reliability it was meant to enhance.

This article examines the dual nature of via-in-pad: its significant thermal benefits, the reliability risks it introduces, the manufacturing processes that mitigate those risks, and the design guidelines that help you get the thermal advantage without the reliability penalty.

What Is Via-in-Pad and Why Is It Used

In Traditional Pcb routing, vias are placed adjacent to component pads and connected by a short trace — the "dog-bone" fanout. This approach keeps the pad surface intact for soldering but adds routing area and increases the thermal path length between the component and the internal copper plane.

Via-in-pad places the via directly within the pad. The component solder joint makes contact with the pad surface, which has a via barrel passing through it to internal layers. This eliminates the dog-bone trace, saves routing space, and — critically for power components — provides a direct, short thermal path from the component junction to internal copper planes.

Where Via-in-Pad Is Commonly Applied

• BGA land pads: Fine-pitch BGAs (0.5 mm and below) often cannot be routed with dog-bone fanout because the routing channels between pads are too narrow. Via-in-pad with Microvias is the standard solution for breaking out these high-density arrays.
• QFN and DFN thermal pads: The center Thermal Pad under a QFN package is the primary Heat Dissipation path. Via-in-pad arrays within this pad connect it to internal copper planes, providing the lowest thermal resistance path for heat to escape.
• Power component pads: MOSFETs, voltage regulators, and power ICs that dissipate significant heat benefit from via-in-pad on their thermal tabs, connecting directly to buried copper for heat spreading.
• RF pad vias: RF components sometimes require grounded pads with very short, low-inductance connections to the ground plane. Via-in-pad provides the shortest possible path, minimizing parasitic inductance.

Thermal Performance Benefits

The thermal advantage of via-in-pad is substantial and well-documented. By providing a direct conductive path through the PCB dielectric to internal copper planes, via-in-pad reduces the thermal resistance between the component and the heat spreading layer, lowering junction temperature for a given power dissipation.

Quantifying the Thermal Benefit

The thermal resistance of a via-in-pad connection has two components: the via barrel (copper cylinder) and the connection to the internal plane (copper spreading). For a typical 0.3 mm diameter via with 25 µm plating in a 1.6 mm board, the via barrel thermal resistance is approximately 7-10°C/W. A 5-via array reduces this to 1.4-2.0°C/W. For a component dissipating 5 W, this via array alone can reduce the junction temperature by 7-10°C compared to a design where heat must conduct laterally through the pad and then through a dog-bone trace to a via.

For QFN thermal pads, the benefit is even more pronounced. A QFN power stage with a 3×3 mm Thermal Pad and a 5×5 array of 0.3 mm filled vias can achieve total thermal resistance (junction to ambient via the PCB path) that is 30-50 percent lower than the same component with no Thermal Vias, and 15-25 percent lower than with dog-bone vias placed around the pad perimeter.

Thermal Spreading Effect

Via-in-pad does more than just conduct heat vertically. By connecting the component pad directly to an internal copper plane, it activates the plane's lateral heat spreading capability. Copper's Thermal Conductivity (385 W/m·K) is roughly 1,000 times higher than FR4 (0.35 W/m·K). Once heat reaches the internal plane, it spreads rapidly across the plane area, effectively increasing the Heat Dissipation surface far beyond the component pad footprint.

This spreading effect means that a via-in-pad array under a small component can leverage a large internal ground or power plane as a heat sink. A 5×5 mm QFN thermal pad connected through vias to a 50×50 mm internal copper plane can achieve effective thermal performance comparable to a small external heatsink — without the cost, space, and assembly complexity of an attached heatsink.

Reliability Risks: The Solder Wicking Problem

The primary reliability risk of via-in-pad is solder wicking — the tendency of molten solder to flow into the via barrel during reflow, draining solder away from the joint between the component termination and the pad surface. This reduces the effective solder volume at the joint, creating weak or open connections.

How Solder Wicking Occurs

During reflow, when the solder paste melts and becomes liquid, capillary forces draw the molten solder into any available cavity. An open via barrel is a cylindrical cavity that exerts strong capillary action on the liquid solder. The smaller the via diameter, the stronger the capillary effect (capillary pressure is inversely proportional to radius). Solder can wick down the entire via barrel, filling it from top to bottom, and leave insufficient solder on the pad surface to form a reliable joint with the component.

The severity of wicking depends on several factors:

• Via diameter: Smaller vias have stronger capillary action but less volume to fill. The net effect depends on the ratio of via volume to available solder paste volume.
• Solder paste volume: If the paste deposit on the pad is generous, some solder can wick into the via without depleting the joint. If the paste volume is marginal, even a small amount of wicking can cause insufficient solder at the joint.
• Via fill state: An open (unfilled) via wicks solder freely. A via that is pre-filled with copper or epoxy before assembly has no cavity for solder to enter, eliminating wicking entirely.
• Reflow profile: Longer time above liquidus gives more time for capillary flow. A fast reflow profile with short TAL reduces wicking.

Consequences of Solder Wicking

• Insufficient solder at the joint: The solder joint between the component and the pad has reduced volume, resulting in a thin, weak connection with poor mechanical strength and elevated electrical resistance.
• Void formation: Solder that wicks into the via and then solidifies can trap flux and gas, creating voids within the via barrel that weaken the via's electrical and thermal connection.
• Tombstoning and misalignment: Asymmetric wicking — where one via in a pad wicks more solder than another — creates unbalanced surface tension forces that can lift one end of a two-terminal component or shift a BGA ball off its pad.
• Inconsistent joint quality: Wicking is variable — some vias may fill completely while others do not, creating joint-to-joint inconsistency that is difficult to predict or control.

Via Fill Methods: Solving the Wicking Problem

The manufacturing solution to solder wicking is to fill the via before component placement, eliminating the cavity that draws solder away from the joint. Two primary fill methods are used in production.

Copper Fill

Copper fill electroplates copper into the via barrel, creating a solid copper plug. After plating, the board surface is planarized (ground flat) to remove copper overburden and create a smooth, flat pad surface for soldering.

Advantages:

• Solid copper fill has the highest Thermal Conductivity of any fill method, preserving the via's thermal performance.
• Excellent electrical conductivity — copper-filled vias carry current with minimal resistance.
• No coefficient of thermal expansion (CTE) mismatch — the fill material is the same as the via plating and pad copper, so thermal cycling does not create stress at the fill interface.
• Best long-term reliability — no risk of fill material cracking, delaminating, or outgassing.

Limitations:

• Higher cost — copper fill requires additional plating time and planarization (back-drilling or grinding).
• Process complexity — the plating must completely fill the via without voids. High aspect ratio vias (depth/diameter > 1) are challenging to fill completely.
• Limited to via diameters that can be reliably filled — typically 0.2-0.5 mm. Very small Microvias may not fill completely.

Epoxy Fill (Conductive or Non-Conductive)

Epoxy fill uses screen-printed epoxy to fill the via barrel. Conductive epoxy contains silver or copper particles to provide electrical and thermal conductivity. Non-conductive epoxy is used when the via only needs to be plugged to prevent wicking, and electrical/thermal conductivity through the fill is not required.

Advantages:

• Lower cost than copper fill — epoxy fill uses standard screen printing equipment.
• Effective at preventing solder wicking — the via cavity is filled before solder paste application.
• Can fill high aspect ratio vias more reliably than Copper Plating.

Limitations:

• Reduced thermal conductivity — even conductive epoxy has thermal conductivity of 5-20 W/m·K, far below copper's 385 W/m·K. For Thermal Vias, this significantly increases the via's thermal resistance.
• Cte Mismatch — epoxy has a different CTE than copper and FR4. Under thermal cycling, differential expansion can create stress at the epoxy-copper interface, potentially leading to cracking or delamination over thousands of cycles.
• Non-conductive epoxy blocks both electrical and thermal conduction through the via. If the via must carry current (e.g., a power ground via), non-conductive fill is unacceptable.
• Outgassing risk — some epoxy fill materials can outgas during reflow, creating voids in the solder joint above the filled via. This risk depends on the epoxy formulation and curing process.

Tented Vias: A Third Option

Via tenting covers the via opening with solder mask, sealing the top of the via barrel. This is the lowest-cost option but has significant limitations:

• Solder mask tenting can prevent solder paste from entering the via during printing, but it does not fill the barrel. If the tent is breached (by solder mask cracking, mechanical damage, or paste pressure), solder can still wick into the open barrel.
• Tenting blocks the via opening on one side, but the via barrel is still hollow. Gas trapped in the barrel can expand during reflow, potentially blowing through the tent and creating solder defects.
• Tented vias do not provide a flat pad surface — the solder mask tent creates a slight dome over the via opening, which can affect component placement accuracy on fine-pitch pads.

Tenting is acceptable for non-critical vias where wicking risk is low (large vias with generous paste volume), but it should not be relied upon for BGA via-in-pad or QFN thermal pad vias where joint reliability is critical.

Thermal Performance Comparison: Filled vs. Unfilled Vias

The choice of via fill method directly affects thermal performance. Here is a quantitative comparison for a typical thermal via scenario: a 0.3 mm diameter, 1.6 mm long via connecting a QFN thermal pad to an internal ground plane.

• Open (unfilled) via: The via barrel provides the thermal path. With 25 µm plating, the copper cross-section is approximately 0.024 mm². Thermal resistance ≈ 10°C/W per via. Solder wicking risk is high — some of the via's thermal benefit may be negated if solder fills the barrel inconsistently.
• Copper-filled via: The entire via cross-section (0.07 mm²) is solid copper. Thermal resistance ≈ 2°C/W per via — a 5× improvement over the open via. Zero wicking risk.
• Conductive epoxy-filled via: The epoxy fill (k ≈ 10 W/m·K) provides some thermal conduction but much less than copper. Effective thermal resistance ≈ 5-7°C/W per via. Zero wicking risk, but Cte Mismatch may affect long-term reliability under thermal cycling.
• Non-conductive epoxy-filled via: The epoxy (k ≈ 0.5 W/m·K) is essentially a thermal insulator. Only the via plating conducts heat. Thermal resistance ≈ 10°C/W per via (same as open via). Zero wicking risk, but no thermal improvement over the plated barrel alone.

The conclusion is clear: for thermal vias under power components, copper fill provides the best thermal performance and the best reliability. Conductive epoxy is a compromise that eliminates wicking but sacrifices significant thermal performance. Non-conductive epoxy eliminates wicking but provides no thermal benefit over an unfilled via.

Reliability Under Thermal Cycling

For applications that experience repeated temperature cycling — automotive, aerospace, industrial, and outdoor electronics — the long-term reliability of the via-in-pad connection under thermal stress is as important as its initial thermal performance.

Copper-Filled Via Reliability

Copper-filled vias have the best thermal cycling reliability because the fill material is metallurgically bonded to the via plating and the pad copper. There is no material interface with CTE mismatch. Under thermal cycling, the copper fill, via barrel, and pad expand and contract together, maintaining mechanical and electrical integrity through thousands of cycles.

Industry testing has demonstrated that copper-filled via-in-pad structures survive 1,000+ thermal cycles (-40°C to +125°C) with no detectable degradation in joint resistance or thermal performance. This makes copper fill the preferred choice for Class 3 and automotive applications.

Epoxy-Filled Via Reliability

Epoxy-filled vias have lower thermal cycling reliability due to CTE mismatch. Typical PCB epoxy has a CTE of 40-60 ppm/°C below Tg and 150-250 ppm/°C above Tg, while copper's CTE is 17 ppm/°C. This mismatch creates shear stress at the epoxy-copper interface with every temperature cycle.

Over hundreds or thousands of cycles, this stress can cause:

• Microcracking at the epoxy-copper interface.
• Delamination of the epoxy fill from the via barrel.
• Outgassing from cracked epoxy that contaminates the solder joint.

The severity depends on the cycling temperature range, the epoxy formulation, and the via geometry. For moderate cycling ranges (0°C to +85°C), conductive epoxy fill is generally reliable for 500+ cycles. For extreme ranges (-40°C to +125°C or wider), copper fill is strongly preferred.

Solder Joint Reliability with Via-in-Pad

The solder joint itself — the connection between the component termination and the pad surface — is affected by via-in-pad in several ways:

• Pad flatness: Planarized (capped) copper-filled vias provide a flat pad surface that is equivalent to a non-via pad. This ensures consistent solder paste deposition and reliable joint formation. Epoxy-filled vias that are not properly planarized may have a slight depression or bump at the via location.
• Local thermal mass: The via-in-pad creates a local increase in thermal mass (copper fill) or a local decrease (open via, which has less copper than the surrounding pad). This affects the local reflow profile — the solder above a copper-filled via may heat slightly slower than solder on the surrounding pad, creating minor wetting timing differences. In practice, this effect is small and rarely causes problems.
• Pad rigidity: Copper-filled vias stiffen the pad locally, which can affect the solder joint's ability to accommodate CTE-mismatch strain between the component and the board. In some cases, a slightly more compliant pad (without via-in-pad) can absorb differential expansion better, reducing solder joint fatigue. However, for most applications, the thermal benefit of via-in-pad outweighs this consideration.

Design Guidelines for Via-in-Pad

For BGA Land Pads

• Use via-in-pad only when routing density requires it. For pitch ≥ 0.65 mm, dog-bone fanout with standard vias between pads is usually possible and avoids the cost and complexity of via fill.
• For pitch ≤ 0.5 mm, via-in-pad with microvias is typically necessary. Specify copper fill for all BGA via-in-pads to prevent wicking and ensure reliability.
• Via diameter should not exceed 60-70 percent of the pad diameter. A via that is too large relative to the pad leaves insufficient Annular Ring for reliable soldering.
• Place the via at the center of the pad for symmetric heat extraction and consistent solder wetting.

For QFN Thermal Pads

• Use a via array rather than a single via. A 3×3, 4×4, or 5×5 array distributes heat more uniformly and provides lower total thermal resistance.
• Specify copper fill for all thermal pad vias. The thermal performance penalty of epoxy fill is significant for power components, and the wicking risk of open vias is unacceptable for the large solder volume on a thermal pad.
• Via diameter for thermal pads can be larger than for BGA signal pads — 0.3-0.5 mm is typical. Larger vias have more copper cross-section and lower thermal resistance.
• Consider via pitch carefully. Too many vias can weaken the pad (creating a Swiss-cheese effect) and reduce the solderable surface area. A typical rule is that vias should not remove more than 30 percent of the pad area.
• Solder paste stencil design for thermal pads with via-in-pad requires special attention. Use a segmented paste pattern (multiple small deposits rather than one large one) to prevent excessive paste from being drawn into the via array.

For Power Component Thermal Tabs

• Maximize the number of thermal vias within the available pad area. For a power MOSFET with a 2×1 mm thermal tab, a 2×1 or 3×2 via array may be all that fits, but every via helps.
• Use the largest via diameter that fits within the pad without reducing the Annular Ring below the minimum for reliable soldering.
• Connect thermal vias directly to an internal copper plane — do not route them to traces. The plane provides the lateral heat spreading that makes the via array effective.

Manufacturing Cost Impact

Via-in-pad with fill adds cost compared to standard vias or dog-bone routing. Understanding the cost components helps you make informed trade-offs.

• Copper fill: Adds 10-20 percent to board cost for typical BGA and QFN designs, depending on the number of filled vias. The cost comes from additional plating time, planarization, and the tighter process control required for void-free fill.
• Epoxy fill: Adds 5-10 percent to board cost. Lower than copper fill but provides less thermal benefit.
• Via tenting: Adds negligible cost — it uses the standard solder mask process. However, the reliability risk may result in higher costs downstream (rework, field failures).

For most designs with BGA or QFN components, the cost of copper-filled via-in-pad is easily justified by the improvement in first-pass yield (fewer solder defects), thermal performance (no need for external heatsinks), and long-term reliability (fewer field failures). The cost savings from avoiding rework and field returns typically exceed the incremental board cost within the first production run.

FAQ

Can I use via-in-pad without fill for non-critical applications?

For low-power, non-safety-critical applications where the component dissipates less than 0.5 W and thermal performance is not critical, open via-in-pad without fill may be acceptable. The wicking risk is still present, but with generous solder paste volume and a reflow profile that minimizes time above liquidus, the impact may be manageable. However, you should validate this approach with first-article inspection (X-ray) to confirm that joint quality is acceptable before committing to production.

Does via-in-pad always improve thermal performance?

Almost always, yes — provided the vias are filled with copper. Open (unfilled) vias provide some thermal benefit through the via plating, but if solder wicks into the barrel, the thermal connection becomes inconsistent. Epoxy-filled vias improve thermal performance over no vias but underperform copper fill. The only scenario where via-in-pad does not improve thermal performance is when the internal layer the via connects to has no copper plane at that location — the via terminates in Dielectric Material and has no spreading path. Always ensure thermal vias connect to an actual copper plane.

How many thermal vias do I need under a QFN?

There is no single answer — it depends on the component power dissipation, the internal plane area, the acceptable junction temperature rise, and the available pad area. As a starting point, use a via array that covers 20-30 percent of the thermal pad area, with via diameter of 0.3-0.4 mm and pitch of 0.8-1.0 mm. Then verify with Thermal Simulation or measurement that the junction temperature is within limits. Adding more vias beyond the point where the internal plane is effectively engaged yields diminishing returns.

What about via-in-pad on high-frequency signal pads?

Via-in-pad on high-frequency signal pads (RF, high-speed digital) introduces a capacitive stub — the via barrel below the pad acts as a capacitive element that can degrade Signal Integrity. For signal pads, via-in-pad should be used only when routing requires it, and the via should be back-drilled (controlled-depth drilled from the opposite side to remove the unused portion of the barrel) if the stub length would degrade signal performance. For thermal-only pads (QFN thermal pads, power tabs), capacitive stubs are not a concern because these connections are DC or low-frequency.

Is there a reliability difference between microvias and through-hole vias in pad?

Yes. Microvias (laser-drilled, typically ≤ 0.15 mm diameter, connecting only 1-2 layers) have lower aspect ratios and smaller volumes than through-hole vias. This makes them easier to fill completely with copper and less prone to fill voids. However, microvias have less copper cross-section and higher thermal resistance per via than a larger through-hole via. For thermal applications where via count is limited by pad area, larger (0.3-0.5 mm) through-hole vias with copper fill generally provide better thermal performance than microvias. For BGA signal routing, microvias are preferred because they fit within fine-pitch pads and are more cost-effective to fill.

Via-in-pad is a powerful design technique that can significantly improve thermal performance and routing density — but it demands careful implementation to avoid reliability problems. The key is to match the via fill method to the application requirements: copper fill for thermal vias and critical BGA pads where maximum thermal performance and long-term reliability are required; conductive epoxy fill as a cost compromise for less demanding applications; and via tenting only for non-critical vias where wicking risk is low. Always specify via fill explicitly in your fabrication notes, verify fill quality with cross-section or X-ray, and validate the thermal performance of your via-in-pad design with measurement or simulation before committing to production. When done correctly, via-in-pad delivers the thermal and routing benefits your design needs without the reliability compromises you cannot afford.

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